FPGA Acceleration of Bolt Inspection Algorithm for a High-Speed Embedded Machine Vision System (ICCAS 2019)

Most machine vision systems for bolt inspection are implemented on PC-based platforms for an embedded platform have limited computation performance. In order to implement a bolt inspection machine vision system on an embedded platform with advantages of high power-efficiency and lower cost as well as improved computation power, this paper proposes accelerating bolt inspection algorithms on an SoC of Embedded CPU and FPGA using Hardware-Software codesign methods. First, image processing algorithms for bolt defect detection are designed and implemented on an embedded CPU (ARM Cortex-A53). Then, the computation load of each algorithms is analyzed to find key functions responsible for CPU bottleneck. These heavy loaded functions are identified as morphology, threshold, and center-finding, which are then accelerated using parallel processing on an FPGA. The proposed bolt machine vison algorithms of combining processing software (embedded CPU) and programmable logic (FPGA) were implemented on an SoC platform (Xilinx ZCU-104). Experiments conducted on images of normal and defected bolts showed that the proposed system could accelerate calculation speeds by up to 18.9 times, and the overall system by 1.3 times, compared to the software-only embedded CPU platform.