High-Speed Digital Bus Testing using Automatic Test- Markup Language (ATML)

Department of Defense (DoD) military systems designed to attack, protect, and provide tactical advantages to the warfighter increasingly push technological advances. Systems and subsystems share data at high rates to make quick decisions. Because of the rapid advancements in technology, the DoD Family of Testers (FoT) are unable to validate units under test (UUT) that use high-speed digital buses. Current and developing solutions to solve this problem are done in a closed architecture designed specifically for one DoD automatic test system (ATS). Technology Service Corporation's Automatic Test System (TSCATS) is being developed as a high-speed digital bus augmentation capability to the DoD FoTs leveraging IEEE standards to provide an open architecture framework. The discrete system can be remotely triggered and applicable to a wide range of DoD FoTs. The TSCATS utilizes a commercial off-the-shelf (COTS) PXIe hardware platform and a software Test Executive (TE) capable of parsing an automatic test mark-up language (ATML IEEE Std. 1671) test description (TD) document and using synthetic instruments to deliver and test high-speed communication protocols. Benefits to this approach include reduced life-cycle, TPS development, and re-host costs while providing DoD an augmented test capability for their ATS environment. The DoD is increasingly incorporating ATML as its standard language in describing all aspects of automated test systems and automatic testing. The sub-standard for IEEE Std. 1671, IEEE Std. 1671.1 - Standard for Automatic Test Markup Language Test Description, identifies and documents the necessary components for describing the testing procedure for a UUT. For a Test Program Set (TPS) developer, the test description provides important test information in developing software to validate a DoD UUT. The TSCATS hardware platform TE, Test Forge, provides test sequencing, parameter validation, data reporting, error handling, and UUT and ATE monitoring solutions. Test Forge is designed independently of specific underlying requirements of UUTs or test station capabilities. It is designed to provide a flexible architecture that allows developers to add or extend functionality. The Test Forge ATML TD tools provide an interface for test developers to load ATML test descriptions and automatically generate software test shells for development, parameter files, test sequences, and executable build specifications for the TPS software. The TSCATS hardware platform will incorporate a synthetic high-speed instrumentation module capable of exchanging test signals with the UUT controlled by Test Forge and can be connected to any ATE, DoD or commercial. The reconfigurable instrumentation module currently provides speeds up to 12.5 Gbps data rates, meeting signal requirements for high-speed communication protocols such as 10 GbE, SATA, USB, and Serial RapidIO. The platform uses COTS hardware based on industry standard practices for low-cost and easier upgrades. The TSCATS is designed to provide DoD a low-cost, open architecture, high-speed bus tester with ease of UUT re-hosting.