A 18-24 GHz Compact Single Stage Amplifier with 13 ± 0.5 dB gain, OP3dB of +19 dBm and 19% PAE for Radar Applications in Tower 180 nm CMOS

This paper proposes a modified differential cascode amplifier topology for mm-wave applications requiring wideband amplification, flatness and compact integration area. The proposed topology was used to create a single stage power amplifier with +13 dB small-signal gain ±0.5 dB flatness over 18 - 24 GHz. The power amplifier load-pull and biasing were optimized to reach a maximum PAE around 3 dB compression to minimize AM-PM variation and maximize performance-to-reliability ratio in large phased array transmitters. At 3 dB compression, an output power of +19 dBm with a peak PAE of 19% was measured around 18 GHz. Respectively, at 8 dB compression a peak power of +20 dBm is achieved and is over +19 dBm up to 24 GHz. The circuit demonstrates one of the smallest core area (0.16 mm
²
) and excellent power density. The proposed topology presents currently a record small signal gain per stage at this technology node (f
_T
/f
_max
of 59/65 GHz). The presented amplifier topology can be used repetitively and reliably to create wide-band amplifiers with state-of-the-art gain, flatness and return loss over small area. The circuit was realized using Tower's 180 nm CMOS.