An optimization method for placement of decoupling capacitors on printed circuit board

This paper investigates the optimal placement of decoupling capacitors on printed circuit boards (PCB). This method minimizes the impedance characteristics at the power supply in the specified frequency range in order to find the optimal decoupling capacitor position. In this method, the PCB is modeled via the partial element equivalent circuit (PEEC) model approach to handle the 3D structures, and the Krylov-subspace technique is used to obtain the impedance characteristics in the frequency domain efficiently.