Novel methodology for mid-frequency delta-I noise analysis of complex computer system boards and verification by measurements

This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The mid-frequency noise is caused by the current fluctuations of on-chip switching activity. The method provides very fast and efficient descriptions of highly complex packaging structures during every system development phase, which allows fast and accurate noise simulations with SPEED97. The simulation results have been confirmed by measurements to within 5%.