Combined MPSoC Task Mapping and Memory Optimization for Low-Power

The combination of processor and memory optimization in low-power multiprocessor system-on-chip software design unfolds new opportunities and allows for better results. This paper discusses the steps towards such a design flow with respect to required individual building blocks. Presented experimental results for a quad-core platform and a set of representative benchmarks support our proposed approach. On average, we achieve 8.6 % power reduction and 16.2 % less energy consumption compared to a state-of-the-art performance-optimized baseline using an industrial SW mapping framework.