Realization of Resource Efficient Block RAM Based Eight Bit Adder in FPGA

Delay time of any combinational or sequential circuit realized in field programmable gate array (FPGA) is the propagation delay of the circuit. Researchers attempt to develop optimized solutions for the applications developed using it. In this way, importance is given in realizing an optimized adder circuit. This work has proposed an 8-bit adder circuit designed using Block RAM. The result of addition of two 8-bit data is stored in the Block RAM. 8-bit adder developed using Look-up-table (LUT) indicated that an `n' bit adder circuit requires (2ⁿ + 2ⁿ) memory locations. This work has developed 8-bit adder using both LUT and Block RAM. Synthesis result showed that 8-bit addition is performed in 4.894ns when Block RAM is used in the design. The time required to perform LUT based 8-bit adder is 5.729ns.