Advanced Logic Level Design Methodology for a Secure DPA Resistant FPGA

The detection of both software and introduced faults by differential fault analysis attacks is used to protect the circuit that can be added in to the cryptographic systems. The trustworthy of the specified devices can be improved by using protection to the circuit, it is also responsible to suffer more power reduction and the other methods. The attacks of power analysis attacks and differential fault analysis attacks are a section of side channel attacks; it is used to give power consumption measurements, responsible for giving preservation of secret information stored in crypto-system. In this paper, to increase the security of crypto-system against PAAs, we introduce the secure double rate register (SDRRs) as a register transfer level (RTL) countermeasures standard (AES)-128 designs is exploited in the SDRR. The generation of random and real information safeguarded to protect the both combinational and sequential logics by calculating combinational path. The previous technique of RTL countermeasure requires the fake combinational path to generate the random information; our proposed technique does not need this duplication process. To execute a protected DPA resistant crypto-system, a new design methodology is described in this paper. An experimental result indicates a maximum time reduction in the power consumption fluctuations.