Work-in-Progress: DeVos: A Learning-based Delay Model of Voltage-Scaled Circuits

Dynamic voltage and frequency scaling (DVFS) is a typical method to reduce energy consumption of circuits. However, it may cause timing errors if the frequency is not set properly under scaled voltages. To alleviate this issue, this paper proposes DeVos, a supervised learning model that can predict dynamic delay of voltage-scaled circuits based on their input workload. We measure the dynamic delay using switching activity generated through gate-level simulation of a post place-and-route design in TSMC 45nm process. We then look for features in the input data that influence dynamic path sensitization. Using these features we apply random forest to construct a predictive model trained and tested using random data. Across a wide range of voltage levels, DeVos achieves on average a mean absolute percentage error (MAPE) of less than 5%. To our best knowledge, DeVos is the first dynamic delay model of voltage-scaled circuits and can be used to enable accurate dynamic voltage and frequency scaling.