An integrated low-noise CMOS PLL frequency synthesis

A fully monolithic prototype frequency synthesis based on a phase-locked loop (PLL) is described. To overcome the affections of noise, all the circuits of the synthesizer use a differential architecture and the digital parts designed by state logic. The voltage control oscillator (VCO) utilizing a modified ECL scheme provides low noise and operates over a wide range of power supply voltage. The experimental VCO has a frequency range from 700 MHz to 1.05 GHz. The test chip was designed in a standard 0.6 /spl mu/m n-well CMOS technology, consuming 95 mW at maxim frequency from a 5 V supply.