Design of 6T SRAM Cell Using Optimized 20 nm SOI Junctionless Transistor

The semiconductor industry has shifted to the System-On-Chip (SoC) platform. The short channel effects (SCEs) turns out to be noticeable with the transistor scaling. Consequently, deteriorating the transistor performance. The severe SCE degrades the performance of Static-Random-Access-Memory (SRAM) in SoC chip. The 6T SRAM suffers from the read stability problem (RSNM), which the data might be wrongly retrieved during read operation. In this paper, the designs of 6T SRAM cell using 20 nm Silicon-on-Insulator (SOI) Junctionless transistor (JLT) is proposed. The introduction of SOI technology is to isolate the bulk substrate from the gate, thereby, reducing the junction parasitic capacitance. Hence, higher speed performance could be achieved. The device structure of 20 nm SOI-JLT is simulated by using Sentaurus Device Editor (SDE) module of the Synopsys Sentaurus TCAD tool. Then, the optimization of SOI-JLT device is performed through the L9 Taguchi method. Predictive Technology Model (PTM) SPICE model generator tool is used to generate the SPICE model of the SOI-JLT. Then, the simulation of SOI-JLT based 6T SRAM cells are carried out. The static noise margin (SNM) of 6T SRAM cells are extracted and compared with the published data. The significant findings of this work show that the proposed 20nm SOI-JLT based 6T SRAM cells has enhanced the retention SNM by more than 100% from other's 6T SRAM cell (published data). It also shows that the read and write stability of the proposed 20nm SOI-JLT based 6T SRAM cell is improved by more than 20% from the published data.