Design and Analysis of Low Leakage SRAM cell at 45nm Technology

In this modern electronic era of miniaturization of circuitry, there is tremendous need to have devices with low power usage. Power consumption is one of the problematic considerations which affect designing of portable devices and high- performance ICs. In deep submicron regimes, due to scaling of channel length, gate oxide thickness and threshold voltage, leakage becomes an issue of grave concern. Subsequently, proper identification and modeling of various leakage components is crucial for estimating and reducing leakage power dissipation, especially in low power applications. An SVL switch can work either by reducing supply voltage to cell in standby state (USVL or type-1) or by increasing voltage of ground node connected to cell in standby state (LSVL or type-2) or by a combination of both (type-3). Along with SVL technique, VTCMOS technique can also be used simultaneously. A combination of both the techniques provides considerable reduction in leakage dissipation. The type-3 technique turns out to be the most effective technique among the three for leakage reduction and static power reduction. All simulations are carried out in CADENCE VIRTUOSO tool at 45nm technology.