SRAM Issues and Scrutiny at 45nm having Low Leakage Power and Leakage Current

In this paper an overview of conventional 6T SRAM and its limitations are discussed. Then a brief discourse for different design issues in a 6T static random access memory (SRAM) that is scathing element in SoC and VLSI applications. The cell is reported with high SNM 398.67mV, leakage power of 112.49nW, leakage current of 3.48μA and delay 20.77fs. This paper shows SRAM stability which is scrutinized by process variations and leakage issues for cell augmentation. Read and write stability is analyzed; results are obtained and verified using 45nm technology. The originality and contribution of this paper is in its high SNM, RSNM and WSNM (measured using butterfly approach) with low leakage power and current. The previous results have lower WSNM by 8.44%, T
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variation of 27.08%, the SNM is 360mV, leakage power 232.2μW and high delay 8.57ps disrupting cell stability. The post layout simulations and measurements proof the effectiveness of designed cell.