Novel Tree Based Priority Encoder Design Technique

Priority Encoders (PEs) are quite critical component for digital system design. Authors have proposed a tree based scalable PE design methodology. Observing the modularity, regularity and locality concepts the proposed design technique is very simple using which any (n × k) PE can be implemented with the help of pre functional/tested (n/2 × m) PE (where m=k-1). Using the proposed PE mechanism authors have demonstrated the implementation of (4×2) PE, (8×3) PE, (16×4) PE, (32×5) PE, (64×6) PE, (128×7) PE, (256×8) PE, (512×9) PE, (1024×10) PE, (2048×11) PE and (4096×12) PE. Authors have created HDL IP for PE design which can be mapped for fabless industry or ASIC application. Further authors have comprehensively analyzed the designed PEs for 12 different C_Load capacities and 11 different temperature ranges. These designs are implemented on Xilinx-Zybo board for comprehensive evaluation. The results prove the accuracy, effectiveness and easiness of the proposed PE design methodology. PEs implemented using proposed technique have higher operating frequencies as compared to PEs reported in prior art. The Path-delay and area is improved by 26.6% and 6.7% respectively when compared with previous design. The logic-delay of implemented 64×6PE, 32×5PE, 16×4PE is 34ps, 17ps and 13ps respectively. The 64×6PE circuit has a maximum PDP of 1.35zWS indicating an efficient performance. From the circuit simulation results the proposed design methodology is proved to be efficient.