Design and Performance Analysis of 6T SRAM on 130 nm Technology

CMOS devices are being scaled down for better performance in areas like power dissipation, speed, size and reliability. It is important to reduce the energy usage while increasing the access-time speed, to encourage the growth of memory technology. SRAM finds extensive applications in system-on-chip (SOC) designs. Though various other topologies have been proposed in literature, the core of this paper reviews the standard 6T SRAM bitcell and provides a systematic insight into the structure and analysis techniques using 130nm CMOS technology node. The functioning of the cell has been studied through basic operations like read, write and hold. Static noise margins for read, write and hold operations have been measured from the Voltage Transfer Characteristics and N-curve. Comparisons have also been made between the butterfly curve and N-curve to measure noise margins through simulations. The write noise margin has been further studied through methods like Bitline and Wordline Sweep.