Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code

In prior researches, low-density-parity-check (LDPC) code is applied on high-speed magnetic random-access-memory (MRAM) for a better correctable bit error rate (CBER). However, on another emerging memory, resistive random-access-memory (RRAM), reset hard breakdown errors have high-reliability log-likelihood ratio (LLR) which significantly degrades LDPC code soft decision CBER and decoding iterations. To solve this issue, two schemes, improved-LLR and reset-check-reverse-flag (RCRF) concatenating systematic LDPC code (RCRF + LDPC), are proposed. The first scheme increases soft decision CBER by using asymmetric LLRs for matching the distribution of reset hard breakdown errors. In addition, RCRF corrects at least one reset error per array subsection. So, both hard and soft decision CBERs are improved. The best performance is obtained by combining these proposals. The hard decision CBER is increased by more than 50% on a wide range of LDPC code options. Moreover, soft decision CBER is improved by 69% and 51%, respectively, on a 1KB codeword, 0.91 code rate quasi-cyclic-LDPC (QC-LDPC) code, and a 2KB codeword, 0.89 code rate Mackey's code.