Design and Analysis of high Efficient Latched Comparator

Keeping pace with the new era, the necessity for comparator circuit with low power and high speed profile is increasing. In this research, a new latched comparator is proposed and compared with the conventional model. The proposed circuit is designed using PTM model. This circuit is proposed to overcome the difficulties mentioned in the conventional circuits. Different feature sizes (180nm and 32nm) transistor are considered. We have calculated power and delay and they are compared with previously proposed circuits for demonstrating the efficiency of the proposed model. Its power consumption is low compared with others and delay is decreasing with feature size. Also it has higher resolution and load drivability than those conventional approaches.