Analysis of low power novel SRAM design with self-biasing approach for ultra-low power applications

Leakage power dissipation has been an overriding constraint for the digital device, as portable devices contain static random access memory (SRAM) units. The memory units have longer standby mode than the active mode, which further increases the leakage current. In this paper, the literature based on the classification of leakage reduction techniques for low power SRAM has been explored. In order to achieve low leakage power in scaled SRAM cell, we have been proposed a novel SRAM cell with the self-biasing (SB) approach. Four topologies are introduced based on PMOS self-biasing and NMOS self-biasing approach. The proposed design was analyzed and Simulated with cadence virtuoso simulator using gpdk 45 nm technology. The proposed design 1 and design 2 significantly minimizes the leakage power by 78% and 51% respectively as compared to the basic design. However, the proposed designs marginally reduce the signal to noise margin.