Analysis of Low Power SRAM Design with Leakage Control Techniques

In today's digital era, memory is an inevitable part of any integrated device. Also it has a major part in the total circuit power. As the growing concern for portable devices is increasing day by day, the nano-technology is grabbing the eyes of the chip makers. But the drain of power in portable devices which mainly contains static random access memory (SRAM) units is inversely proportional to the technology used. In order to balance this trade off various leakage reduction techniques have been proposed. In this paper we propose a hybrid circuit which involves biasing and power gating techniques to improvise the reduction in leakage power. Simulations have been carried out in Symica DE using 32 nm technology. The hybrid circuit in HOLD state is compared with some of the existing low power designs for leakage power and static noise margin (SNM).The hybrid-1 and hybrid-2 reduced the power leakages by 88.32% and 85.63% respectively and the SNM is increased by 2 times by hybrid-1 while hybrid-2 maintained the same SNM as that of the basic 6T SRAM cell.