High Speed Comparator Design for the Implementation of Successive Approximation Register ADC

In this work, a comparator operating at 400MHz frequency with a resolution of 10 bits is designed. In order to eliminate the effect of offset voltage in the designed comparator circuit, auto-zero technique is used. The fully differential operational amplifier structure is used in the comparator circuit as it prevents common mode distortion. Clock signals and CMOS structures of switch, latch, inverter and full differential operational amplifier structures of the comparator circuit are given in detail. The performance parameters of the designed circuit are realized in Cadence environment with 0.18μm technology.