Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue

In this paper, we present a new 10T design for static random access memory (SRAM). The proposed design simultaneously aims to address stability, power and half select issues. The design metrics such as power, delay, and stability of the proposed design are compared with 7T, 11T, and 9T SRAM cells. It is observed that the proposed design reduces read and write power by 27.69% and 41.72% as compared to 11T and 9T SRAM cell. Furthermore, WSNM of the proposed SRAM is larger as compared to 7T, 9T and 11T. In addition, the RSNM is larger than 7T and 9T. The simulation result confirms that the proposed design is effective for low power application.