Design and Implementation of FBMC/OQAM Transceiver for 5G Wireless Communication System

Recently, Many Multicarrier Communication Techniques (MCT) has been developed to support requirements for next wireless communication, namely the fifth generation (5G) wireless communication. The Filter Bank Multicarrier /Offset Quadrature Amplitude Modulation (FBMC/OQAM) system is one of the proposed modulation schemes for the next wireless communication system because it provides high data rate and it has the benefit of very low side lobes leading to less inter-carrier interference (IC). The main goal of this research is to design and simulate the FBMC/OQAM transceiver physical layer with Square Root Raised Cosine Filter (SRRC) Prototype filter. The FBMC/OQAM transceiver system is built in VHDL for simulation and implementation on an FPGA. Moreover, the Physical layer will be illustrated along with a detailed simulation of the FBMC/OQAM system to study the effect of various design parameters. VHDL will be used for register-transfer level (RTL) description and FPGA synthesis tools will be used for performance analysis of the transceiver. Moreover, The RTL coding of VHDL will be used to provide a high-level design flow for developing and validating the transceiver system. The ISIM Xilinx edition will be used for functional simulation and verification. The performance of transceiver implementation was assessed through some parameters such as resource usage, power usage, latency, and throughput. It is found that the FBMC/OQAM transceiver has good resources usage and power consumption. Then, is possible to conclude that FBMC/OQAM system is a viable candidate waveform for 5G.