SystemVerilog Modeling of SFQ and AQFP Circuits

Exascale computing and its associated increasingly massive amounts of data require increasingly efficient computing platforms; and semiconductor technology is struggling to keep up. Meanwhile, superconducting electronics (SCE) is increasingly gaining interest in both industry and academia as a serious contender to replace silicon for supercomputing. In particular, nonresistively biased single-flux quantum (SFQ) circuits have a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude of higher speed, and adiabatic quantum-flux-parametron (AQFP) circuits possess a theoretical potential of six orders of magnitude reduction in power when compared to the state-of-the-art semiconductor circuits. Unfortunately, the SCE community lacks a reliable design flow. Rather than creating a complete design flow from scratch, it is often more efficient to reuse well-established semiconductor tool flows developed by EDA companies that have benefited from research and development over the past half-century. One of the components of this flow is the hardware description language (HDL) modeling of gates for behavioral and functional simulation of large netlists. The previous HDL models proposed for SCE lack modularity are not compatible with existing CMOS standards, and are overly complex. This article presents SystemVerilog models for SFQ and AQFP gates and the circuits that interface between them. Our models are compatible with standard delay format and commercial simulators. They offer a generalizable modular debugging platform, are elegant and conceptual, and can capture many circuit parameters, environmental effects, and advanced SCE phenomena.