A Novel Design of Ternary Level SRAM cell using CNTFET

CNTFETs present a new alternative of ternary operation against the usual binary operation of Si CMOS technology. Ternary logic offers several advantages over binary logic such as increased bit density and energy efficiency due to increased functionality possible in a given chip area. This paper presents a novel design of ternary Static Read Access Memory (SRAM) using Carbon Nano-tube Field Effect Transistors (CNTFETs). Advantages of CNTFET technology along with a brief discussion on Stanford university model of CNTFET used for simulation of SRAM are discussed. The proposed design and performance parameters such as Power, Delay, Static Noise Margin (SNM) along with circuit performance under VT variations are discussed. With a supply voltage of 0.9V, we obtained good SNM values with the use of fewer transistors along with better delay and power figures.