Design and implementation of Efficient Direct Memory Access (DMA) Controller in Multiprocessor SoC

In Multiprocessor System on Chip (MPSoC), power and area optimization is a major concern. In this paper, efficient Direct Memory Access (DMA) controller which suits the MPSoC environment is designed and implemented. The design is synthesized using Cadence Encounter RTL Compiler targeted to 45nm artisan_slow_normal.lib standard technology libraries. The implemented design has given power advantage ranging 22% to 23% and area advantage of 19% to 20% for source and destination address generator respectively when compared with the existing method which is also designed for comparison. The design is a synthesizable core which can be extended to be part of any MPSOC design suitable for communication and signal processing SoC.