A comparison study of on-chip and optimized gate inductor of an LNA

In a receiver frontend, LNA (Low noise amplifier) is an essential block to amplify required low power signal buried under noise. According to Frii’s formula Noise Factor of the transceiver primarily depends on the NF (Noise Figure) & gain of first RF component i.e. LNA. Traditionally, the most critical design parameter of LNA belongs to input matching and low noise figure. Subsequently, it has been observed that, design of CMOS based LNA design critically depends on inductors present in the design. In present paper a comparative study has been done between on-chip inductor and optimized gate inductor based LNA. This is validated in Cadence Virtuoso Tool using TSMC 180 nano-meter technology CMOS process with power supply of 1.8 volts. Approach for design of narrow band cascaded and cascoded Low Noise Amplifier with inductor source degenerated technique is used at 2.45 GHz.