Beyond the Limits: SHA-3 in Just 49 Slices

The National Institute of Standards and Technology (NIST) chose in 2012 the winner of the third competition to decide a new hashing standard, establishing the new Secure Hash Algorithm-3 (SHA-3). Multiple FPGA implementations were published during the standardization process to compare performances, but also after the official announcement, improving and optimizing the state of the art further. In this work, we present new implementations to improve several different aspects from previous works. We introduce a new row-oriented architecture, never used before in the "race" for the most lightweight SHA-3 FPGA implementation. Featuring this new row-based processing, we present two architectures with different area-frequency trade-offs?. We use FPGA resources never considered before in the literature, and discuss the limitations they present. In addition to this, we present a pipelined implementation aiming for the best compromise between area and throughput. As a result, our lightweight implementation uses 44% fewer resources than the current state of the art. Moreover, our efficiency-tailored implementation is 70% more efficient than the previous best work on the Virtex-6 platform. In essence, in this work, we present the smallest and the most efficient SHA-3 FPGA tailored implementations to date.