Sampling Rate Reduction for Digital Predistortion of Broadband RF Power Amplifiers

In this article, we present a novel technique to build digital predistorters that can linearize broadband power amplifiers (PAs) using reduced sampling rates. In contrast to conventional digital predistortion (DPD) where oversampling is necessary to avoid aliasing effect, the proposed method cancels the aliasing distortion using a sliced multistage cancellation scheme. A large reduction of sampling rate can be achieved in digital implementation of DPD, significantly reducing power consumption and implementation cost. Experimental results show that a DPD with a sampling rate of merely 1.5×, instead of 5×, signal bandwidth, can still produce satisfactory performance within the linearization bandwidth but consume only one-third of power, compared with that using the conventional approaches. The proposed technique provides a promising solution for the next-generation 5G systems, where large signal bandwidths are required.