A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS

This paper presents an 8.4 ps 500 MS/s 4-bit successive approximation register time-to-digital converter (SAR-TDC). The TDC utilizes both the rising and falling edges of the cyclic signals defining the time input to perform time-to-digital conversion thereafter to low both the frequency of the cyclic signals and the power consumption of the system generating these signals by 50%. Pre-skewing is utilized to improve the resolution of the digital-to-time converter (DTC) subsequently the resolution of the TDC. Both the design and performance of the double-edge SAR TDC are compared with those of a corresponding single-edge SAR TDC. The TDCs was designed in a TSMC 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show at 500 MS/s, the TDC achieves a SFDR of 37.6, a SNDR of 25.5 dB, a resolution of 8.4 ps while consuming 0.86 mV.