Design of a 180 nm CMOS transceiver for implantable wireline communication, achieving 800 Mbps at BER<1e-12 with 22.4 dB of channel loss

Wireline communication for implantable devices is an emerging topic in circuits and systems research, motivated by progress in electronic interfaces that are used in experimental neuroscience and emerging medical applications. Special considerations are required for maintaining robust operation in a physiological environment, including low voltage signaling over specialized interconnect that experiences high channel loss. This manuscript reports on the design and simulation of a full wireline transceiver in 180 nm CMOS, which achieves 800 Mbps at BER <; 1e-12 with 22.4 dB of channel loss, with power utilization of 10.8 pJ/bit in the TX and 2.3 pJ/bit in the RX with +/-500 mV supplies. The design was simulated with S-parameters extracted from characterization of a 0.5 meter implantable wireline link immersed in saline. Implementation in the 180 nm process, which is desirable for integration with neural recording and stimulation electronics, presents design challenges for achieving efficient high speed communication circuits with low voltage operation.