Novel, Low-power ECRL-CMOS Interface Circuit

Adiabatic logic families typically use signal waveforms very different to standard static CMOS logic. Pulsed power-clocks driving the circuit lead to pulsed or sinusoidal signals that cannot be easily interfaced with existing CMOS logic structures. This work focuses on a novel interface circuit that converts existing signals in ECRL (efficient charge recovery logic) to signals typical of standard CMOS logic. Energy losses are evaluated based on switching speed and the nature of the incoming bitstream to the interface. Comparison to an existing reference interface is included, weighing the advantages and disadvantages inherent to both interfaces. All circuits were designed, extracted, and simulated in 180nm CMOS technology. The proposed interface effects energy savings in unique conditions when compared to the reference work and exploits unique properties of the adiabatic logic signaling for proper functionality.