Design and Analysis of Energy Efficient Reversible Logic based Full Adder

Conventional digital systems incur information loss due to erasure of bits during logic operations resulting in remarkable amount of energy/power loss. Reversible computations nullify the information loss by retaining bits at the output. In arithmetic and logic computational structures, adders are the fundamental and performance determining component. In this paper an energy efficient low power reversible full adder is proposed, which is a combination of Feynman gates and a Fredkin gate. This paper proposes a comprehensive analysis and estimation of energy dissipation in reversible circuits. Cadence Virtuoso schematic editor is used to experimentally validate the models. The proposed adder effectively reduces ancilla inputs by 50%, garbage outputs by 50%, quantum cost by 33.33% and transistor count by 16.67% in comparison with full adder architectures present in literature.