Influence of parasitic structures on the ESD performance of a pure bipolar process

The purpose of this work is to show that parasitic structures greatly affect the ESD performance of a bipolar process. More especially, the existence of a parasitic diode in parallel to the protection transistor in the input stages of a pure bipolar IC leads to a low ESD performance for HBM stresses, while the ESD performance for MM stresses is high. Suppression of this diode significantly increases the ESD performance for both types of stresses.