Hardware Architecture for CSMA/CA Algorithm for IEEE 802.15.4 LR-WPANs

The rapid growth in the latest IoT and wireless technologies are demanding low power, high reliability, and low latency applications. IoT makes use of IEEE Std 802.15.42015 which supports low latency applications. In this paper, the combined hardware architecture for both slotted and unslotted CSMA/CA channel accessing algorithm has been proposed. We have proposed a new hardware design for CSMA/CA that is efficient as compared to the earlier existing hardware. The performance of the proposed architecture is analyzed in XC3S700AN device for various input message bit sizes by using Verilog HDL. The maximum clock frequency is increased by 87% as compared to the best available design for 2-bit message input.