Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops

The paper presents and discusses the timing modeling approach for digital Radiation-Hardness by Design (RHBD) ΔTMR flip-flops. The basic fault-tolerant Triple Modular Redundancy (TMR) flip-flop architecture and the Single Event Transient-tolerant variant for the datapath (ΔTMR) are briefly introduced. The main focus is set on proper timing library modeling and timing check characterization respectively, as these are required in the digital design flow. The analyses are made with usage of a 130nm high performance BiCMOS technology node as a case study for the paper.