Chip-Level ESD Verification Using Graph-Theory Based Approach

An Electrostatic Discharge (ESD) simulation and verification flow that has been demonstrated on a real design in bipolar technology is presented in this work. The described flow can be used to verify the level of ESD robustness of integrated circuit (IC) designs. Secondly, it is possible to identify the ESD current paths between any two nodes in the design, and the flow can determine which devices will fail in the case of a catastrophic ESD event. The presented flow is based on a graph-theory Floyd-Warshall algorithm and previously defined breaking voltage (BV) models.