An FPGA-Based Data Receiver for Digital IC Testing

FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and round-trip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.