A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors

The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% - 9.05% and in 6T SRAM 2.51% - 4.76% and 3.77% - 5.64% decrease for storing 0 and 1 respectively.