Experimental Investigation for Enhancement of Timing Margin of Single-ended Parallel Bus By Optimizing Phase Response of Signal Modes

This paper proposes an approach that compensates the phase difference of even and odd modes considering the overall channel characteristics to enhance the timing margin. Specifically, this approach involves the method of how to determine the optimal amount of compensation capacitance required to prevent crosstalk and minimize jitter. The appropriate compensation capacitance determined by the proposed method change the propagation delay of odd mode so that the odd mode signal matches the even mode one. Two types of test vehicles were fabricated to verify the effectiveness of this proposal, and the optimal performance predicted by our theoretical calculation was successfully validated by consistent simulation and experimental results. The phase matching in the frequency domain was confirmed by measuring the S parameters, and the improvement of signal integrity in the time domain was verified by the post-processed eye diagram using the measured S parameters. Furthermore, in order to consider the complexity in the real system, the effect of multi-drop topology in a typical memory channel was also investigated. The results demonstrate that the proposed method is an intuitive and efficient way to minimize far-end crosstalk in a high-speed memory channel.