Design Of 3 Bit Adder Using 6 Transistors In Mentor Graphics

The concept of this design is to reduce number of transistors to implement an 3 bit adder. In this project, the existing 12 transistors 3 bit adder into 6 transistors three bit adder and design can be implemented by using Mentor graphics 130nm technology. The 6T three bit adder is constructed using basic PMOS and NMOS logic, in the 6T three bit adder, twice 2T XOR module sum is generated, and by the NMOS and PMOS pass transistor logic devices carry is generated. . Due to this design, the area occupied on silicon area will be reduced. By comparing to other designs such as 28 transistor, 14 transistor and transmission gate adder logic designs, it can optimize power.