High Energy Efficiency FPGA-Based Accelerator for Convolutional Neural Networks Using Weight Combination

Convolutional neural network (CNN) has achieved excellent achievements in the field of image recognition. Because of the better energy efficiency and fewer development cycle, FPGA has been widely used as the implementation platform of CNN. The quantized CNN reduces the demand for storage and transmission bandwidth, and is easier to be implemented on FPGA platforms. And the weights of the quantized network contain a lot of repetitions and zeros. The repeatability and sparsity of these weight parameters can be well utilized in the hardware implementation of CNN. In this paper, a CNN accelerator is designed and implemented on the Virtex-7 FPGA, and the test network is AlexNet with 17 unique weights after quantization. By using weight combination method, the accelerator redesigned the calculation pattern of the processing elements (PEs), reducing the multiplication by 92.25%. The experiment result shows that our accelerator achieves 179 GOPS under 200 MHz clock frequency. The energy efficiency of 32.72 GOPS/Watt is obtained by combining the new PE with the systolic array architecture.