Image analysis and partitioning for FPGA implementation of image restoration

In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adaptation onto a reconfigurable platform. We present our hardware design for the image restoration algorithm and our estimations on the performance of the FPGA implementation. Our results show that the speedup gained for practical systems varies between 6.5 and 10.2 for different images. We also propose and evaluate a statistical method for analysis of images subject to restoration to gain an insight into the convergence time of the restoration algorithm. Based on this we explore a image partitioning strategy using this statistical analysis.