Algorithms Development and Verification for Next Generation On-board Clock Monitoring and Control Unit

The on-board timing subsystem is the key part of the Global Navigation Satellite System (GNSS) payloads. An Engineering Model (EM) of the Galileo on-board Clock Monitoring and Control Unit for the next generation (called “CMCU+”) has been developed. To meet the CMCU+requirements tasks of algorithms have been carried out: to generate the output frequency signal based on an ensemble of input clocks with optimized performance and improved robustness by clock anomalies handling. In addition, the algorithms should be feasible for an on-board implementation. In this paper, we present the design, development, and in particular performance verification of algorithms for CMCU+.