Access-Aware Self-Adaptive Data Mapping onto 3D-Stacked Hybrid DRAM-PCM Based Chip-Multiprocessor

The number of cores on chip-multiprocessor is increasing due to the higher computation demand and technology advancement. Therefore, chip-multiprocessor requires larger on-chip memory as well as a high-end interconnection network. DRAM memory architect using 3D-stacked technology is a promising candidate; however, as the DRAM memory size increases, it suffers due to the overheads related to the DRAM row refreshes. Larger capacity hybrid memories architect using DRAM and PCM technology is a good solution to tackle this problem. Moreover, to utilize the benefits of the large capacity 3D-stacked hybrid memory, studies need to consider the data placement and memory management schemes for these memories. In this work, we have considered a 3D-stacked hybrid DRAM-PCM memory based chip-multiprocessor system. Moreover, we performed an access-aware self-adaptive run-time page mapping to reduce the remote access latency as well as DRAM refresh overheads of the chip-multiprocessor. Our technique performs on an average of 4% better (in terms of the execution time) as compared to the base-case (in base-case, chip-multiprocessor uses non-coherent 3D-stacked DRAM only memory). Whereas, energy consumption due to the DRAM refresh reduced by an average of 49% as compared to the base-case.