TOSwitch: Programmable and High-Throughput Switch Using Hybrid Switching Chips

The future of networking switches and routers foresees in two key features: Programmability and Throughput. In this letter, we propose a Traffic Offload Switch (TOSwitch) model for such a versatile switch, using different breeds of switching chips, an ASIC and an FPGA, to achieve the above two key features. Our TOSwitch model is useful in many real-world use cases. The TOSwitch gives line-rate throughput and low latency for current and future network protocols. In our simulation on Xilinx Zynq 7000 (ONetSwitch45) FPGA board, the results show that the traffic offload model does not introduce considerable overhead in terms of latency, throughput and switching chip resources.