Hardware Architecture For A Shift-Based Parallel Odd-Even Transposition Sorting Network

Sorting is one of the most frequently executed routines on modern computers. Such algorithms are classically implemented as software programs and can contribute significantly to the overall execution time of a process. In this respect, implementing sorting algorithms in hardware can dramatically increase the overall performance of the applications embodying them. This paper proposes an optimized hardware architecture for a parallel Odd-Even transposition sorting network, on field programmable gate array (FPGA) based embedded systems. This implementation introduces a modification of the classical Odd-Even Transposition sorting algorithm. This modification is a shift-based approach offering high flexibility for general purpose applications. The proposed architecture results in increasing overall performance by minimizing hardware resource utilization, increasing the operating frequency and reducing complexity. Simulation and synthesis results demonstrates that the proposed architecture is minimal in size, can operate on odd and even length arrays, capable of sorting arrays of length larger than two times the number of available processors, and can begin the sorting process at data input.