A Branch Predictor Design to Improve Prediction Rate by Reducing Index Aliasing in Application Processors

The current processors of mobile device are designed in a reduced instruction set computer (RISC) architecture. The branch instruction, which occupies 20 to 30% of RISC pipeline structure, is one of the main reasons of processor performance degradation. Failure to predict a branch causes a pipeline flush called a stall, and the processor will not be able to process the command during that cycle. Various branch predictors have been proposed; the conventional schemes such as global and local predictor have the disadvantages of wasting memory or having low prediction rates. Global predictors have low prediction rate due to index aliasing. Index aliasing is a phenomenon that makes wrong predictions due to overlapping indexes accessing the predictor. The proposed scheme is intended to reduce the occurrence of index aliasing by performing more XOR and addition operations in the index generation process than in conventional schemes. As a result, the proposed method has 0.69%p better prediction rate than the conventional method, which improves the processor performance. In this paper, the simulation was executed using the SimpleScalar 3.0 simulator and the benchmark program SPEC CPU2000. The experimental results show that when the cache size is 128KB currently used for smart phones, the proposed scheme has the best prediction.