A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions

Network Functions Virtualization (NFV) has received considerable attention in the past few years, both from industry and academia, due to its potential for reducing capital and operational expenditures, thus enabling faster innovation in networks. NFV proposes decoupling network functions from fixed hardware platforms and implementing them as virtual machines on off-the-shelf servers. Although potentially able to provide the mentioned benefits, software-based implementations of compute-intensive network functions still struggle to perform at the desired speed, especially when requiring line-rate processing for ever-faster communication links. To address this, hardware acceleration can be used to improve the throughput and latency of virtualized network functions (VNFs). In order to provide the advantages foreseen for NFV, however, such accelerators cannot be fixed and application-specific hardware, since they need to cope with new VNFs as well as fluctuations in demand. In this context, Field-Programmable Gate Arrays (FPGAs) are particularly suitable, since they are able to provide high-performance implementations of network functions and they are completely reprogrammable, thereby being able to implement different VNFs even after deployment. There have been many recent efforts to enable the use of FPGAs in the NFV context, including efficient implementations of network functions on FPGAs, platforms to manage the integration and coexistence of multiple VNFs on an FPGA, and high-level synthesis tools especially tailored to ease the programming of VNFs for FPGAs. In this work we survey previous work covering these aspects, and discuss the main open research challenges that must be addressed before FPGA adoption in NFV infrastructures becomes effectively seamless and efficient.