Toward Automated Simulink Model Implementation and Optimization using High-Level Synthesis for FPGA

FPGAs have shown great potential in accelerating the execution of a wide variety of workloads, including simulations of physical and electrical systems. However, many users do not possess sufficient expertise in modern digital design techniques to achieve the greatest benefit from FPGA technology and limitations in current commercial tools do not support the simulation of arbitrary models in FPGAs. Toward that end, we present the challenges to implementing Simulink models via high-level synthesis design techniques, the potential benefits of using this approach, and a preliminary tool that demonstrates one key step toward the automated simulation of arbitrary models. Such a tool would enable transparent, automated model translation from a graphical user interface to an FPGA for users without expertise in FPGA-based digital design.