Analyzing Crosstalk-Induced Effects in Rough On-Chip Copper Interconnects

Aggressive scaling of on-chip interconnects results in significantly higher coupling capacitance, which results in crosstalk effects as we enter the end-of-the-roadmap era. Moreover, surface roughness is seen as a major contributor to conductor losses that further exacerbates these crosstalk-induced effects. This article reports an exhaustive analysis of crosstalk-induced effects, considering interconnect surface roughness at current and future technology nodes (i.e., 13 and 7 nm), for on-chip global copper interconnects. The role of repeater insertion in rough interconnects is also presented in our work. For our analysis, we have used an aggressor-victim-aggressor three-line bus architecture and FINFET-based driver circuits with binary input logic. Our results show that surface roughness degrades typical interconnect performance metrics i.e., worst case delay, bandwidth density (BWD), power consumption, and power-delay product. At a 7-nm technology node, average worst case crosstalk delay and power consumption increase by 17× and 9×, respectively, when compared to smooth interconnects. Similarly, due to surface roughness, BWD reduces by nearly 17× for 7-nm global interconnects. For data rates of 0.2 Mb/s, eye height and eye width are reduced by 73% and 54%, respectively, in the worst case scenario for 7-nm global lines. Finally, we showcase the role of repeater insertion in enhancing performance metrics, in which crosstalk delay and power delay products are significantly improved (by 85% and 99%, respectively) at a 7-nm technology node.